Öffentliche Ausschreibung in Erlangen

The work to be performed by contractor is the place and route for digital design parts up to top level based on chip specification, Verilog netlists, SDC synthesis constraint data and physical synthesis floorplans including layout extraction and physical design verification (DRC, LVS). Such work includes definition of the implementation flow and a sufficient documentation of the design implementation.In addition there is work on the Interposer layer in different technologies (silicon or organic) for Chiplet designs to be performed. •All design and implementation work shall be executed in cooperation betweenIIS and contractor by using Cadence (P&R) and Mentor (DRC, LVS) design software on IISservers via remote or on-site access. •The work shall be executed partially remote, partially on site based on projects needs •Cadence design software, technology libraries, standard cella, memory and GPI/O modelaccess as well as IP access will be made available on IIS servers •Mentor Calibre physical design verification